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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-13108-2E
Memory FRAM
CMOS
2 M Bit (128 K x 16)
MB85R2002
DESCRIPTIONS
The MB85R2002 is an FRAM (Ferroelectric Random Access Memory) chip consisting of 131,072 words x 16 bits of non-volatile memory cells created using ferroelectric process and silicon gate CMOS process technologies. The MB85R2002 is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85R2002 can be used for at least 1010 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. The MB85R2002 uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM.
FEATURES
* * * * * * * Bit configuration Read/write endurance Operating power supply voltage Operating temperature range Data retention LB and UB data byte control Package : 131,072 words x 16 bits : 1010 times/bit (Min) : 3.0 V to 3.6 V : -20 C to +85 C : 10 years (+55 C) : 48-pin plastic TSOP (1)
Copyright(c)2007 FUJITSU LIMITED All rights reserved
MB85R2002
PIN ASSIGNMENT
(TOP VIEW)
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE CE2 GND UB LB VCC NC A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC GND I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 VCC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 OE GND CE1 A0
(FPT-48P-M25)
PIN DESCRIPTION
Pin name A0 to A16 I/O1 to I/O16 CE1 CE2 WE OE LB, UB VCC GND NC Address Input Data Input/Output Chip Enable 1 Input Chip Enable 2 Input Write Enable Input Output Enable Input Data Byte Control Input Power Supply Ground No Connection Function
2
MB85R2002
BLOCK DIAGRAM
A0 * * *
Address Latch.
to
Row Dec.
Ferro Capacitor Cell
A16 Column Dec. intCE2 S/A CE2 intCEB LB UB WE OE CE1 intCEB I/O8 * * to I/O1 * * intCE2 intOE intWE intCE2 I/O1 to I/O8 I/O9 to I/O16 I/O16 to I/O9
3
MB85R2002
FUNCTION TRUTH TABLE
Mode CE1 CE2 WE OE LB UB I/O1 to I/O8 I/O9 to I/O16 Supply Current
H Standby Pre-charge X X X Read
X L X X H
X X H X H
X X H X L
X X X H L L H L
X X X H L H L L H L L H L L H L Dout Dout High-Z Dout Dout High-Z Din Din High-Z Din Din High-Z Dout High-Z Dout Dout High-Z Dout Din High-Z Din Din High-Z Din Operation (ICC) High-Z High-Z Standby (ISB)
L
Read (Pseudo-SRAM, OE control*1)
L
H
H
L H L
Write
H L
L
X
L H L
Write (Pseudo-SRAM, WE control*2)
L
H
H
L H
L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance : Latch address and latch data at falling edge, : Latch address and latch data at rising edge *1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read. *2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write.
4
MB85R2002
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage* Input Voltage* Output Voltage* Ambient Operating Temperature Storage Temperature * : All voltages are referenced to GND = 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VCC VIN VOUT TA Tstg Rating Min -0.5 -0.5 -0.5 -20 -40 Max +4.0 VCC + 0.5 VCC + 0.5 +85 +125 Unit V V V
o o
C C
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage* Input Voltage (high)* Input Voltage (low)* Ambient Operating Temperature Symbol VCC VIH VIL TA Value Min 3.0 VCC x 0.8 -0.5 - 20 Typ 3.3 Max 3.6 VCC + 0.5 +0.6 +85 Unit V V V
o
C
* : All voltages are referenced to GND = 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB85R2002
ELECTRICAL CHARACTERISTICS
1. DC CHARACTERISTICS
(within recommended operating conditions) Value Parameter Symbol Test Conditions Unit Min Typ Max Input Leakage Current |ILI| VIN = 0 V to VCC 10 A VOUT = 0 V to VCC, CE1 = VIH or OE = VIH 10 A Output Leakage Current |ILO| 1 Supply Current ICC CE1 = 0.2 V, CE2 = VCC-0.2 V, IOUT = 0 mA* 10 15 mA CE1 VCC-0.2 V CE2 0.2 V*2 Standby Current ISB 10 50 A OE VCC-0.2 V, WE VCC-0.2 V*2 LB VCC-0.2 V, UB VCC-0.2 V*2 Output Voltage (high) VOH IOH = -0.1 mA VCC x 0.8 V IOL = 2.0 mA 0.4 V Output Voltage (low) VOL
*1 : During the measurement of ICC , the Address, Data In were taken to only change once per active cycle. IOUT : output current *2 : All pins other than setting pins should be input at the CMOS level voltages such as H VCC - 0.2 V, L 0.2 V.
2. AC CHARACTERISTICS
* AC TEST CONDITIONS Supply Voltage : 3.0 V to 3.6 V Operating Temperature : -20 C to +85 C Input Voltage Amplitude : 0.3 V to 2.7 V Input Rising Time : 5 ns Input Falling Time : 5 ns Input Evaluation Level : 2.0 V / 0.8 V Output Evaluation Level : 2.0 V / 0.8 V Output Impedance : 50 pF (1) Read Operation Parameter Read Cycle time CE1 Active Time CE2 Active Time OE Active Time LB, UB Active Time Pre-charge Time Address Setup Time Address Hold Time OE Setup Time LB, UB Setup Time Output Data Hold time Output Set Time CE1 Access Time CE2 Access Time OE Access Time Output Floating Time 6 Symbol tRC tCA1 tCA2 tRP tBP tPC tAS tAH tES tBS tOH tLZ tCE1 tCE2 tOE tOHZ (within recommended operating conditions) Value Min 150 120 120 120 120 20 5 50 5 5 0 30 Max 100 100 100 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MB85R2002
(2) Write Operation (within recommended operating conditions) Parameter Write Cycle Time CE1 Active Time CE2 Active Time LB, UB Active Time Pre-Charge Time Address Setup Time Address Hold Time LB, UB Setup Time Write Pulse Width Data Setup Time Data Hold Time Write Setup Time (3) Power ON/OFF Sequence (within recommended operating conditions) Parameter CE1 LEVEL hold time for Power OFF CE1 LEVEL hold time for Power ON Symbol tpd tpu Value Min 85 85 Typ Max Unit ns ns Symbol tWC tCA1 tCA2 tBP tPC tAS tAH tBS tWP tDS tDH tWS Value Min 150 120 120 120 20 5 50 5 120 0 50 5 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns
3. Pin Capacitance
(f = 1 MHz, TA = +25 oC) Parameter Input Capacitance Output Capacitance Symbol CIN COUT Test Condition VIN = GND VOUT = GND Value Min Typ Max 10 10 Unit pF pF
7
MB85R2002
TIMING DIAGRAMS 1. Read Cycle Timing 1 (CE1, CE2 Control)
tRC tCA1 CE1 tPC
CE2 tBS LB, UB tAS A0 to A16 Valid tES OE tCE1, tCE2 I/O1 to I/O16 tLZ tAH
tCA2 tBP
H or L tRP tOHZ High-Z Invalid
tOH Valid Invalid
2. Read Cycle Timing 2 (OE Control)
tCA1 CE1
CE2 tBS LB, UB tAS A0 to A16 Valid tAH
tCA2 tBP
H or L tRC
OE
tRP
tPC
tOE tLZ I/O1 to I/O16 Invalid tOH Valid
tOHZ High-Z Invalid
8
MB85R2002
3. Write Cycle Timing 1 (CE1, CE2 Control)
tWC CE1 tCA1 tPC
CE2 tBS LB, UB tAS A0 to A16 Valid tAH
tCA2 tBP
H or L
tWS WE
tWP
tDS tDH High-Z Data In Valid H or L
4. Write Cycle Timing 2 (WE Control)
tCA1 CE1
CE2 tBS LB, UB tAS A0 to A16 Valid tAH
tCA2 tBP
H or L tWC tWP tPC
WE
tDS tDH High-Z Data In Valid H or L
9
MB85R2002
POWER ON/OFF SEQUENCE
tpd tpu
VCC CE2 3.0 V
VIH (Min)
VCC CE2 3.0 V
VIH (Min)
1.0 V
1.0 V
VIL (Max)
VIL (Max)
CE2 0.2 V
GND GND
CE1 > VCC x 0.8*
CE1 : Don't Care
CE1 > VCC x 0.8*
CE1
CE1
* : CE1 (Max) < VCC + 0.5 V Note : You can choose either of CE1 or CE2, or both for disenable control of the device.
NOTES ON USE
Data that is written prior to IR reflow is not guaranteed to be retained after IR reflow.
ORDERING INFOMATION
Part number MB85R2002PFTN-GE1 Package 48-pin plastic TSOP(1) (FPT-48P-M25)
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MB85R2002
PACKAGE DIMENSIONS
48-pin plastic TSOP(1) Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.50 mm 12.00 x 12.40 mm Gullwing Plastic mold 1.20 mm MAX 0.37 g P-TSOP(1)48-12x12.4-0.50
(FPT-48P-M25)
Code (Reference)
48-pin plastic TSOP(1) (FPT-48P-M25)
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusions. Note 3) Pin widths and pin thicknesses include plating thickness. Note 4) Pin widths do not include tie bar cutting burrs.
0.100.05 (Stand off) (.004.002)
LEAD No.
1
48
INDEX
0.50(.020)
0.22 -0.04
*1 12.000.10
+0.05 +.002
.009 -.002
0.10(.004)
M
(.472.004)
24
25
14.000.20(.551.008)
*2 12.400.10(.488.004)
1.130.07 (Mounting height) (.044.003) Details of "A" part "A" 0~8
+0.05 +.002
0.08(.003)
0.145 -0.03
.006 -.001
0.25(.010)
0.600.15 (.024.006)
C
2003 FUJITSU LIMITED F48043S-c-2-2
Dimensions in mm (inches). Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
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MB85R2002
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
F0709

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